Friday, June 27, 2008

Howto, Synopsys

1. Source the appropriate setup file:

source /usr/local/vlsi/SCRIPTS/synopsys-2004.06-setup.bash

2. Add a ".synopsys_dc.setup" file to your home directory, or assert the setup commands by hand, while running synopsys.
A sample .synopsys_dc.setup file can be found here.
The most important commands in this init file are the:
set target_library
set symbol_library
These variables must be set accordingly to the technology library that you are using.

3. Start synopsys:


4. Read the verilog files:

read -f verilog

Issue the read command for each verilog file of your design. If you have vhdl files, the the "-f" flag, which stands for "-format" should be set to
"vhdl" instead of "verilog".
If there are errors in the source files, then synopsys will report an error.

5. Set the working design


After all of the source files have been read, synopsys treats the *last* module that it read as the working design. This means, that all of the commands
issued after the source have been read, will be executed for the working design and all the modules it includes in hieararchy. If you want to change the
working design, the specify a module using the "current_design" command. Synopsys then will treat the specified module (and all of the modules it
includes in hierarchy) as the working design.

6. Issue the appropriate constraints

Some of the most useful constraint commands are the following:


"Set_drive" sets a "drive" value to the input pins of the working design. "Value" is a value in pF and is typically the drive strength of an inverter
of fanout 4. The exact value of this capacitance can be found in the library datasheet. "Set_load" sets a "load" to the output pins of the working design.
"Value" is expressed in pFand it typically the load of an inverter with fanout 4. The exact value of this load can be found in the library datasheet.

set_false_path [-from ] [-to ]

This command specifies a path which should not be included in the timing analysis. The parameters that it accepts are a "from_list", which can be
anything like input pins, modules, cells, nets, etc. and specifies the startpoints of the false paths, and a "to_list", which specifies the endpoints of the
false paths. It is not mandatory to specify both the startpoints and the endpoints.

set_max_delay [-from ] [-to ]

This commands issues a timing constraint between the "from_list" and the"to_list". The delay between the "from_list" to the "to_list" must not exceed
the "value", which is expressed in ns.


This command instructs synopsys to fix any hold violations on "net", which must be a clock net.


This is an area constraint. The area of the working design must not exceed the area defined by "value". If the "value" is set to 0, the synopsys tries
to minimize the area occupied by the working design.

7. Create a clock

create_clock -name -period

This command specifies the clock and the period of the clock. "Name" can be an arbitrary name and "value" must be the period of the clock in ns.
"clock_net" must be the name of the clock as it is defined in the source files.

8. Compile

compile -map_effort

This command synthesizes and technology maps the working design. can be "low", "medium" or "high".

9. Save the results in database format

write -f db -h -o

This commad saves the design in database format. This format can be used by synopsys later in order to re-synthesize, or timing analyze, or explore
the design in any way. The "-h" flag saves the hierarchy of the design, the "-o" flag specifies the output file and "name.db" can be an arbitrary name.

10. Save the netlist

write -f verilog -hierarchy -o

This command saves the synthesized netlist in verilog format.

11. Write an SDF file

write_sdf -version 1.0

This command writes an SDF file to be used for simulation. "-version" specifies the version of the SDF file, which must be "1.0" in order to be
compatible with the available simulation tools.

12. Perform timing and area analysis


These commands perform a timing and and an area analysis. "report_timing" calculates the delay of the most critical path and reports it's delay.
If this delay does not meet the timing constraints, the a NEGative slack is reported. "report_area" reports the area required by the working design
expressed in um^2.

13. Exit synopsys


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