TSMC Libraries

TSMC Standard Cell Categories => Click on Library name to download

Tech	Process	Library Description	Download
45/40nm	45GS	General Purpose non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN45GSBWP
		General Purpose non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN45GSBWPLVT
		General Purpose non-well biased with UPF and Multi-Voltage support - High Vt	TCBN45GSBWPHVT
		General Purpose non-well biased with UPF, Multi-Voltage and MTCMOS support - Nominal Vt	TCBN45GSBWPCG
		General Purpose non-well biased with UPF, Multi-Voltage and MTCMOS support - Low Vt	TCBN45GSBWPCGLVT
		General Purpose non-well biased with UPF, Multi-Voltage and MTCMOS support - High Vt	TCBN45GSBWPCGHVT
		High Performance non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN45GSBWP12T
		High Performance non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN45GSBWP12TLVT
		High Performance non-well biased with UPF and Multi-Voltage support - High Vt	TCBN45GSBWP12THVT
		High Performance non-well biased with UPF, Multi-Voltage and MTCMOS support - Nominal Vt	TCBN45GSBWP12TCG
		High Performance non-well biased with UPF, Multi-Voltage and MTCMOS support - Low Vt	TCBN45GSBWP12TCGLVT
		High Performance non-well biased with UPF, Multi-Voltage and MTCMOS support - High Vt	TCBN45GSBWP12TCGHVT
	40LP	General Purpose non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN40LPBWP
		General Purpose non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN40LPBWPLVT
		General Purpose non-well biased with UPF and Multi-Voltage support - High Vt	TCBN40LPBWPHVT
		Coarse Grain MTCMOS Library - 9T - Nominal Vt	TCBN40LPBWPCG
		Coarse Grain MTCMOS Library - 9T - Low Vt	TCBN40LPBWPCGLVT
		Coarse Grain MTCMOS Library - 9T - High Vt	TCBN40LPBWPCGHVT
		High Performance non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN40LPBWP12T
		High Performance non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN40LPBWP12TLVT
		High Performance non-well biased with UPF and Multi-Voltage support - High Vt	TCBN40LPBWP12THVT
		Coarse Grain MTCMOS Library - 12T - Nominal Vt	TCBN40LPBWP12TCG
		Coarse Grain MTCMOS Library - 12T - Low Vt	TCBN40LPBWP12TCGLVT
		Coarse Grain MTCMOS Library - 12T - High Vt	TCBN40LPBWP12TCGHVT
65nm	G Plus	Nominal Vt	TCBN65GPLUS
		Low Vt	TCBN65GPLUSLVT
		High Vt	TCBN65GPLUSHVT
		Nominal VT with MTCMOS support	TCBN65GPLUSCG
		Low VT with MTCMOS support	TCBN65GPLUSCGLVT
		High VT with MTCMOS support	TCBN65GPLUSCGHVT
		General Purpose non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN65GPLUSHPBWP
		General Purpose non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN65GPLUSHPBWPLVT
		General Purpose non-well biased with UPF and Multi-Voltage support - High Vt	TCBN65GPLUSHPBWPHVT
	Low Power	Nominal Vt	TCBN65LP
		Low Vt	TCBN65LPLVT
		High Vt	TCBN65LPHVT
		Special Cells - Dual Flip-Flops - Nominal Vt	TCBN65LPDF
		Special Cells - Dual Flip-Flops - Low Vt	TCBN65LPDFLVT
		Special Cells - Dual Flip-Flops - High Vt	TCBN65LPDFHVT
		Nominal VT with MTCMOS support	TCBN65LPCG
		Low VT with MTCMOS support	TCBN65LPCGLVT
		High VT with MTCMOS support	TCBN65LPCGHVT
		General Purpose non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN65LPHPBWP
		General Purpose non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN65LPHPBWPLVT
		General Purpose non-well biased with UPF and Multi-Voltage support - High Vt	TCBN65LPHPBWPHVT
		General Purpose non-well biased with MTCMOS support - Nominal Vt	TCBN65LPHPBWPCG
		General Purpose non-well biased with MTCMOS support - Low Vt	TCBN65LPHPBWPCGLVT
		General Purpose non-well biased with MTCMOS support - High Vt	TCBN65LPHPBWPCGHVT
		High Performance non-well biased - Nominal Vt	TCBN65LPBWP12T
		High Performance non-well biased - Low Vt	TCBN65LPBWP12TLVT
		High Performance non-well biased - High Vt	TCBN65LPBWP12THVT
		High Performance non-well biased with MTCMOS support - Nominal Vt	TCBN65LPBWP12TCG
		High Performance non-well biased with MTCMOS support - Low Vt	TCBN65LPBWP12TCGLVT
		High Performance non-well biased with MTCMOS support - High Vt	TCBN65LPBWP12TCGHVT
		LP process with dual 1V/1.2V devices Nominal Vt	TCBN65LPG
		LP process with dual 1V/1.2V devices High Vt	TCBN65LPGHVT
		7 Tracks - non-well biased with UPF and Multi-Voltage support - Nominal Vt	TCBN65LPBWP7T
		7 Tracks - non-well biased with UPF and Multi-Voltage support - Low Vt	TCBN65LPBWP7TLVT
		7 Tracks - non-well biased with UPF and Multi-Voltage support - High Vt	TCBN65LPBWP7THVT
90nm	General Purpose (G)	Nominal VT with Multi-VDD support	TCBN90GHP
		Low VT with Multi-VDD support	TCBN90GHPLVT
		High VT with Multi-VDD support	TCBN90GHPHVT
		Nominal VT with MTCMOS support	TCBN90GHPCG
		Low VT with MTCMOS support	TCBN90GHPCGLVT
		High VT with Multi-VDD support	TCBN90GHPCGHVT
		Nominal Vt with Back Bias support	TCBN90GHPWB
		Low Vt with Back Bias support	TCBN90GHPLVTWB
		High vt with Back Bias support	TCBN90GHPHVTWB
		7 Tracks - non-well biased with Multi-VDD support - Nominal Vt	TCBN90GBWP7T
		7 Tracks - non-well biased with Multi-VDD support - Low Vt	TCBN90GBWP7TLVT
		7 Tracks - non-well biased with Multi-VDD support - High Vt	TCBN90GBWP7THVT
		Overdrive - Nominal Vt	TCBN90GHPOD
		Overdrive - Low Vt	TCBN90GHPODLVT
		Overdrive - High Vt	TCBN90GHPODHVT
	High Performance (GT)	Nominal Vt	TCBN90GTHP
		Low Vt	TCBN90GTHPLVT
		High Vt	TCBN90GTHPHVT
	Low Power (LP)	Nominal VT with Multi-VDD support	TCBN90LPHP
		Low VT with Multi-VDD support	TCBN90LPHPLVT
		High VT with Multi-VDD support	TCBN90LPHPHVT
		Ultra High Vt	TCBN90LPHPUHVT
		Nominal Vt with Back Bias support	TCBN90LPHPWB
		Low Vt with Back Bias support	TCBN90LPHPLVTWB
		High Vt with Back Bias support	TCBN90LPHPHVTWB
		High Density with Back Bias support - Nominal Vt	TCBN90LPHDBWP
		High Density with Back Bias support - Low Vt	TCBN90LPHDBWPLVT
		High Density with Back Bias support - High Vt	TCBN90LPHDBWPHVT
		High Density with Back Bias support - Ultra Low Vt	TCBN90LPHDBWPULVT
		High Density with Back Bias support - Nominal Vt	TCBN90LPBWP7T
		High Density with Back Bias support - Low Vt	TCBN90LPBWP7TLVT
		High Density with Back Bias support - High Vt	TCBN90LPBWP7THVT
		Nominal VT with MTCMOS support	TCBN90LPHPCG
		Low VT with MTCMOS support	TCBN90LPHPLVTCG
		High VT with MTCMOS support	TCBN90LPHPHVTCG
130nm	General Purpose	Nominal Vt	TCB013GHP
		Low Vt	TCB013GHPLVT
		High Vt	TCB013GHPHVT
	Low Voltage	Nominal Vt	TCB013LVHP
		High Vt	TCB013LVHPHVT
		Over Drive 1.2V	TCB013LVHPOD
		Over Drive 1.2V, High Vt	TCB013LVHPODHVT
	Low Power	Nominal Vt	TCB013LPHP
		Low Vt	TCB013LPHPLVT
150nm	General Purpose	Nominal Vt	TCB015GHD
	Low Voltage	Nominal Vt	TCB015LVHD

TSMC Standard I/O Categories => Click on Library name to download

Tech	Process	Core Voltage	I/O Voltage	Configuration	Download
45nm	Bond Pads	N/A	N/A	Bond Pads	TPBN45V
	General Purpose	0.9V	2.5V; over-drive to 3.3V	Staggered Universal Standard I/O	TPFN45GSGV2OD3
			1.8V	Staggered Universal Standard I/O	TPFN45GSGV18
			1.8V; 2.5V tol	Staggered Universal Standard I/O	TPZN45GSGV18
65nm	Low Power	1.2V All	2.5V; 3.3V tol.	Staggered Universal	TPZN65LPGV2
			All	Linear and Staggered Universal Pads	TPBN65V
			2.5V	Linear Universal	TPDN65LPNV2
			2.5V; 3.3V tol.	Linear Universal	TPDN65LPNV2OD3
90nm	General Purpose	1.0V	3.3V; 5V tol.	Staggered Universal	TPZN90GV3
	Bond Pads	N/A	N/A	In-Line and Staggered Universal	TPBN90V
	Low Power	1.2V	3.3V	In-Line	TPDN90LPNV3
130nm	General Purpose	1.2V	2.5V	Linear Universal	TPD013NV2
			3.3V	Linear Universal	TPD013NV3
			3.3V; 5V tol.	Staggered Universal	TPZ013GV3
	Low Power	1.5V	2.5V	Linear Universal	TPD013LPNV2
			3.3V	Linear Universal	TPD013LPNV3
	Low Voltage	1.0V-OD	3.3V; 5V tol.	Staggered Universal	TPZ013LODGV3
	Bond Pads	All	All	Staggered Universal Pads	TPB013GV
				Linear Universal Pads	TPB013NV

Ubuntu 8.04下安装Synopsys DC 2007

研究探索了好长一段时间，终于在Ubuntu 8.04下成功安装synopsys dc2007.03-SP5。

网上有许多教程但都不是很详细，因此发出来，高手就见飘过，仅供新手学习参考。

1)首先安装installer.

我选的installer是1.8版. 直接解压缩到你想安装的目录就可以.我是安装到/home/mars/EDA/Synopsys/installer

2)接下来安装scl

scl是synopsys的license管理器,这里我选择安装的是10.9.1d版本.这个版本也是直接解压缩到目标目录.

同样安装在/home/mars/EDA/Synopsys/scl.

我用的系统是Ubuntu 8.04，这里选择那个Linux的压缩包就可以.

3)然后安装DC2007.

将DC2007 的common和 linux平台文件解压缩到同一目录下.解压之后会有一个syn.taz文件

到installer目录里执行 ./installer -gui 启动installer的图形安装界面.(这里提一下：有可能因为权限问题执行不了，我把home/mars/EDA整个目录权限改了就好了)

按照提示选择 .taz文件即将目录指向那个syn.taz所在的目录,一路next,就可以安装上DC2007了.

4)DC2007的license以及设置

这一步很关键！参考了网上几篇DC的license设置和环境的设置,最后成功了！

首先是license. 这里我是用EFA-LicGen0.4b和sssverify来产生license的.

把license放到你想存放的目录. 我的是放在/home/mars/EDA/Synopsys/license目录里。

然后打开用户目录下的.bashrc文件设置环境变量,在末尾加上如下内容：

###############################################################################
alias lmli2='/home/mars/EDA/Synopsys/scl/linux/bin/lmgrd -c /home/mars/EDA/Synopsys/license/license.dat -l /home/mars/syn_lic.log'
export SYNOPSYS=/home/mars/EDA/Synopsys
export LM_LICENSE_FILE=27000@mars
export LM_LICENSE_FILE=$SYNOPSYS/license/license.dat
export PATH=$SYNOPSYS/bin:$PATH
alias dv=$SYNOPSYS/bin/design_vision
###############################################################################

其中的路径要根据你自己安装和设置的具体路径修改. .设置完后重启,在终端运行lmli2启动license, 在/home/mars/目录下的syn_lic.log文件会记录license启动的情况.

OK,马上运行dv& 看吧,此时应该能进入dc了.如果没问题,那么dc_shell-t 等能运行. 若还提示有问题,看错误提示进行修改.

Howto, Synopsys

1. Source the appropriate setup file:

source /usr/local/vlsi/SCRIPTS/synopsys-2004.06-setup.bash

2. Add a ".synopsys_dc.setup" file to your home directory, or assert the setup commands by hand, while running synopsys.
A sample .synopsys_dc.setup file can be found here.
The most important commands in this init file are the:
set target_library
set_link_library
set symbol_library
These variables must be set accordingly to the technology library that you are using.

3. Start synopsys:

dc_shell

4. Read the verilog files:

read -f verilog

Issue the read command for each verilog file of your design. If you have vhdl files, the the "-f" flag, which stands for "-format" should be set to
"vhdl" instead of "verilog".
If there are errors in the source files, then synopsys will report an error.

5. Set the working design

current_design

After all of the source files have been read, synopsys treats the *last* module that it read as the working design. This means, that all of the commands
issued after the source have been read, will be executed for the working design and all the modules it includes in hieararchy. If you want to change the
working design, the specify a module using the "current_design" command. Synopsys then will treat the specified module (and all of the modules it
includes in hierarchy) as the working design.

6. Issue the appropriate constraints

Some of the most useful constraint commands are the following:

set_drive
set_load

"Set_drive" sets a "drive" value to the input pins of the working design. "Value" is a value in pF and is typically the drive strength of an inverter
of fanout 4. The exact value of this capacitance can be found in the library datasheet. "Set_load" sets a "load" to the output pins of the working design.
"Value" is expressed in pFand it typically the load of an inverter with fanout 4. The exact value of this load can be found in the library datasheet.

set_false_path [-from ] [-to ]

This command specifies a path which should not be included in the timing analysis. The parameters that it accepts are a "from_list", which can be
anything like input pins, modules, cells, nets, etc. and specifies the startpoints of the false paths, and a "to_list", which specifies the endpoints of the
false paths. It is not mandatory to specify both the startpoints and the endpoints.

set_max_delay [-from ] [-to ]

This commands issues a timing constraint between the "from_list" and the"to_list". The delay between the "from_list" to the "to_list" must not exceed
the "value", which is expressed in ns.

set_fix_hold

This command instructs synopsys to fix any hold violations on "net", which must be a clock net.

set_max_area

This is an area constraint. The area of the working design must not exceed the area defined by "value". If the "value" is set to 0, the synopsys tries
to minimize the area occupied by the working design.

7. Create a clock

create_clock -name -period

This command specifies the clock and the period of the clock. "Name" can be an arbitrary name and "value" must be the period of the clock in ns.
"clock_net" must be the name of the clock as it is defined in the source files.

8. Compile

compile -map_effort

This command synthesizes and technology maps the working design. can be "low", "medium" or "high".

9. Save the results in database format

write -f db -h -o

This commad saves the design in database format. This format can be used by synopsys later in order to re-synthesize, or timing analyze, or explore
the design in any way. The "-h" flag saves the hierarchy of the design, the "-o" flag specifies the output file and "name.db" can be an arbitrary name.

10. Save the netlist

write -f verilog -hierarchy -o

This command saves the synthesized netlist in verilog format.

11. Write an SDF file

write_sdf -version 1.0

This command writes an SDF file to be used for simulation. "-version" specifies the version of the SDF file, which must be "1.0" in order to be
compatible with the available simulation tools.

12. Perform timing and area analysis

report_timing
report_area

These commands perform a timing and and an area analysis. "report_timing" calculates the delay of the most critical path and reports it's delay.
If this delay does not meet the timing constraints, the a NEGative slack is reported. "report_area" reports the area required by the working design
expressed in um^2.

13. Exit synopsys

exit