Interfaces in SystemVerilog

Connectivity across different design modules in Verilog is accomplished through port connections for each interface signal in instantiations. For large designs, this is not very productive as it involves redundant instances and signal declarations and is prone to error.

To resolve this issue, SystemVerilog adds a powerful interface construct to encapsulate the communication between blocks i.e. multiple signals are grouped together to form a single port. The signals declared in the interface definition is in a single location so that any changes in the interface can be captured accurately modifying only once instead of multiple modules as in Verilog. All the modules using this interface need only declare a single interface type port rather than multiple signals. An example of SV interface is below

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SV:

1. // AHB Interface Definition
2. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
3. // These external signals (hclk, hresetn can be implicitly connected between modules
4. wire [31:0] ahb_hdata;
5. wire [31:0] ahb_addr;
6. logic ahb_hwrite;
7. logic [1:0] ahb_htrans;
8. logic [2:0] ahb_hsize;
9. logic [2:0] ahb_hburst;
10. logic ahb_hready;
11. logic [1:0] ahb_hresp;
12. endinterface
14. // Top level Module
15. module ahb_top (input logic ahb_hclk, ahb_hresetn);
17. ahb_bus bus (
18. .ahb_hclk(ahb_hclk),
19. .ahb_hresetn(ahb_hresetn) ); // instance of interface
21. arm_core arm_inst (
22. // ahb_bus ports
23. .bus (bus),
24. // other ports
25. .port1 (port1) // not part of the interface
26. ... );
28. ahb_slave ahb_slave0 (
29. .bus (bus) );
31. dma_master dma_master_inst (
32. .bus (bus),
33. // Other ports
34. ---
35. );
37. on_chip_mem on_chip_mem_inst (
38. .bus (bus),
39. // Other ports
40. --
41. );
43. endmodule
45. // Module Definitions
46. module arm_core (
47. ahb_bus bus, // interface port
48. // other ports
49. input logic port1
50. );
51. // functionality
52. endmodule
54. module ahb_slave (
55. ahb_slave bus
56. );
57. logic [1:0] ahb_hsel;
58. logic [31:0] slave_address;
59. // functionality
60. // Referring signals inside interface requires using interface port name
61. assign bus.ahb_addr = (ahb_hsel == 2'b0) ? slave_address; 'z;
62. endmodule
64. module dma_master (
65. ahb_bus bus;
66. // Other ports
67. ---
68. );
69. // functionality
70. endmodule

An interface can also have tasks, functions, parameters, procedural blocks and type declarations to aid in defining the communication protocol. SV interface cannot have a design hierarchy i.e. no modules can be instantiated in the interface. A modport constructs is provided to define the direction for interface port for different modules. Selecting the appropriate modport for each module can be accomplished during either module definition or during module instance as shown in example below.

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SV:

1. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
2. wire [31:0] ahb_hdata;
3. wire [31:0] ahb_addr;
4. logic ahb_hwrite;
5. logic [1:0] ahb_htrans;
6. logic [2:0] ahb_hsize;
7. logic [2:0] ahb_hburst;
8. logic ahb_hready;
9. logic [1:0] ahb_hresp;
11. modport master ( inout ahb_hdata,
12. output ahb_haddr,
13. output ahb_hsize,
14. input ahb_hready,
15. ---
16. );
18. modport slave ( inout ahb_hdata,
19. input ahb_haddr,
20. input ahb_hsize,
21. output ahb_hready,
22. ---
23. );
24. endinterface
26. module ahb_top (.. );
28. ahb_bus bus (...);
29. dma_master dma_master_inst (bus.master); // Use the master modport view
30. ahb_slave ahb_slave0 (bus.slave); // Use the slave modport view
32. endmodule
34. // Alternatively, modport construct can be used in module definition
35. module ahb_slave (ahb_bus.master bus);
36. endmodule

If no modport is associated with a module, by default all net types are inout and all variable types are ref.

A generic interface port defines the port type using the keyword interface instead of using a name of a specific interface type - the advantage is being able to connect the module to different interfaces. Unlike Verilog, no interface port can be left unconnected and SV .name and .* connection rules can be also be used for interface instances.

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SV:

1. module ahb_slave (interface bus); // generic interface port
2. ahb_slave ahb_slave0 (bus.slave);

SystemVerilog allows tasks and functions to be declared within interface definitions known as interface methods. The task or function has the same syntax as when declared in a module. Using these interface methods, the communication protocol details can be embedded within the interface definition itself.

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SV:

1. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
2. wire [31:0] ahb_hdata;
3. wire [31:0] ahb_addr;
4. logic ahb_hwrite;
5. logic [1:0] ahb_htrans;
6. logic [2:0] ahb_hsize;
7. logic [2:0] ahb_hburst;
8. logic ahb_hready;
9. logic [1:0] ahb_hresp;
11. // Task defined internal to interface
12. task slave_read ( input logic [31:0] raddr);
13. // ...
14. endtask
16. endinterface

Interface methods can also be imported if they are not defined within the interface definition itself. If an interface is connected using modport construct, then the import keyword is used to specify the method. Alternative way is to add the task keyword next to the import and also include function arguments - this is required if the task is exported from an external module.

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SV:

1. interface ahb_bus (input logic ahb_hclk, ahb_hresetn); // Interface can have ports.
2. wire [31:0] ahb_hdata;
3. wire [31:0] ahb_addr;
4. logic ahb_hwrite;
5. logic [1:0] ahb_htrans;
6. logic [2:0] ahb_hsize;
7. logic [2:0] ahb_hburst;
8. logic ahb_hready;
9. logic [1:0] ahb_hresp;
11. modport slave ( import slave_read, // simplest way of importing tasks
12. inout ahb_hdata,
13. input ahb_haddr,
14. input ahb_hsize,
15. output ahb_hready,
16. ---
17. );
19. // Alternative explicit way
20. modport slave ( import task slave_read (input [31:0] addr), // explicit
21. inout ahb_hdata,
22. input ahb_haddr,
23. input ahb_hsize,
24. output ahb_hready,
25. ---
26. );

Importing a task or a function through a modport gives the module access to that task by prepending the interface port name to the task name as with other variables. The imported function/task must be declared as automatic in order to be synthesizable.

SV also includes a way to export a task defined in one module to be available to other modules through an interface. For example, if a function is defined in module A and is exported in the modport construct within interface definition using the export keyword, then the task is available to module B that uses that modport. However, this is not synthesizable and we cannot export the same function from multiple instances of a module.

It is also possible to define a task or function using extern keyword without associating it with the modport construct.

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SV:

1. interface shb_bus (....)
2. ---
3. extern check_parity (input logic [31:0] data); // Not associated with modport
5. modport ahb_slave (...);
7. endinterface
9. module A (...);
11. task check_parity (input logic [31:0] data);
12. // --
13. endtask
14. endmodule

Interfaces can also contain procedural blocks like always, always_ff, parameters and generate statements similar to modules.