Low Power Design -- Lesson 1

Lesson 1: Low-power overview:
Low power design is an increasingly common technique help reduce power dissipation in complex SOCs/ASIC. Power consumption on the chip is consumed both when the circuit is active (dynamic power) and also when it is inactive (static power).
+ Dynamic power is associated by switching of state on nets and cells. Dynamic power is absoluted by switching-frequency, load-capacitance and square of supply voltage:
P(dynamic) = a x F x C x sqr(Vdd)

+ Static power is referred to leakage power. Leakage power consumption is computed by sub-threshold leakage, gate leakage and reverse-bias junction BTBT leakage. For a particular technology process, the gate leakage and reverse-bias leakage are constant. therefore, the leakage current from Drain to Source (into a CMOS-transitor) is defined as static-power consumption:

P(static) = exp (-q x Vth / KT), Vth is threshold-voltage of gate.

So, I think we should learn how the gate delay are computed. The cell delay associated with a transistor is affected by the switching threshold voltage (Vth) and the supply voltage (Vdd):

Delay = Vdd x sqr [(Vdd - Vt), *a]

The high-speed cell delay is reference with lower threshold-voltage and higher supply-voltage. Now a day, when cmos process is scaling down to 65nm and below, the leakage consumption is 40 percent of total power-consumption.