Wednesday, August 20, 2008

Compilation of Included SV files inside Legacy Verilog Files

How to enable compilation of included SV files inside legacy Verilog files
and vice versa?


The switches "" with :+v2k" or
"+verilog2001ext+.v" with "-sverilog" helps in the compilation of
a mix of SystemVerilog and legacy Verilog files. [+v2k]: compiling all files as legacy Verilog files and
files with .sv extension as SV files.

+verilog2001ext+.v [-sverilog]: compiling all files as SystemVerilog files and
files with .v extension as legacy Verilog files.

However, these switches will not apply to the included files, as VCS will consider
the included files to be of the same type as the file where they are included,
irrespective of the extension of the included files.

For example:

`include ""
module top;

interface intf;

With the following command

% vcs +v2k top.v

VCS will issue a syntax error while parsing the included file, since VCS
considers the interface file also as a v2k type file as top.v.

The solution to this is as follows.

Change the file name of top.v to, so that both and
will be parsed with SV syntax. However, this might not be feasible if top.v has
identifiers, which are keywords in SV.

Hence, a more appropriate solution is to use the switch "-extinclude".
This would ensure the following switch combination "" to be effective
for the included files as well.

The same switch is applicable in case of "+verilog2001ext+.v" also.

Now with the following command:

% vcs +v2k top.v -extinclude

The above code will be compiled without any errors.

A similar example for the 2nd situation is:

% vcs -sverilog +verilog2001ext+.v -extinclude

where in, you include a legacy Verilog file dut.v.

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