Tuesday, March 29, 2011

Why use Active-Low reset signal?

Just list some reasons that I think they are correct. Comments are welcome.

1. Board design methods. Usually capacitor circuit is used for Power-On-Reset, such that the voltage at reset pin gradually goes to HIGH value. And by this time all reset activity is done.
2. In CMOS technology, the falling edge of a signal is sharper than a rising one.
3. Library implies.
4. After reset, the reset signal change to high, so the reset signal will not infer by noise.
5. Personal habits

1 comment:

主博客 said...

First item sounds most reasonable:)