在SDK 2.2模擬器中安裝Market

1. 建立AVD，名稱為DAVID_2.2



2. 執行「開始—執行—cmd」，預設會在這個資料夾：
C:\Documents and Settings\%HOME%>

3. 切換目錄至「.android/avd/DAVID_2.2」，指令參考如下：

C:\Documents and Settings\David.Lanz>cd .android
C:\Documents and Settings\David.Lanz\.android>cd avd
C:\Documents and Settings\David.Lanz\.android\avd>cd DAVID_2.2.avd

畫面結果：

C:\Documents and Settings\David.Lanz\.android\avd\DAVID_2.2.avd>



4.複製SDK裡的system.img至此，指令如下：

copy d:\sdk\android\platforms\android-8\images\system.ing



5.在DOS視窗中切換目錄至SDK的tools資料夾，手動啟動模擬器，指令：

cd d:\sdk\android\tools\
emulator -avd DAVID_2.2 -partition-size 96



順利執行模擬器畫面



6.在DOS視窗裡執行指令，取出build.prop檔案。

adb pull /system/build.prop



7.利用文字編輯器開啟編輯build.prop這個檔案，將 ro.config.nocheckin=yes 移除（再最前面加上 mark 符號 #）



8.將剛才取出修改好的檔案存檔，然後執行以下指令將檔案放回去。

adb remount
adb push build.prop /system



9.至此下載Froyo用的Market程式，將之解壓縮後，存放至SDK資料夾(舉例如下)：

D:\SDK\android\tools\GoogleServicesFramework.apk
D:\SDK\android\tools\Vending.apk



10.將步驟9的兩個apk檔案丟入模擬器/system/app資料夾，並刪除SdkSetup.apk，指令如下：

adb push GoogleServicesFramework.apk /system/app
adb push Vending.apk /system/app
adb shell rm /system/app/SdkSetup.apk



11.關閉 Emulator（直接關閉模擬器的視窗即可）。

12.切換目錄至avd的資料夾下：
C:\Documents and Settings\%HOME%\.android\avd\DAVID_2.2.avd>

執行以下指令，刪除由系統產生的「userdata-qemu.img」與「userdata.img」、「cache.img 」這三個檔案刪除，讓Emulator完成初始化。

del userdata*.img cache.img



13.執行「Android SDK and AVD Manager」來啟動模擬器。







大功告成，Market順利在模擬器裡執行。第一次執行Market必須要以google帳號登入，登入後即可下載程式囉。






I can install the market, but I can't install App from it. Maybe someone can help me.

Change your Network Card MAC Address on Ubuntu

There are a lot of reasons you might want to manually set your MAC address for your network card. I won’t ask you what your reason is.

To change this setting, we’ll need to edit the /etc/network/interfaces file. You can choose to use a different editor if you’d like.

sudo gedit /etc/network/interfaces

You should see the line for your network interface, which is usually eth0. If you have dhcp enabled, it will look like this:

auto eth0
iface eth0 inet dhcp

Just add another line below it to make it look something like this:

auto eth0
iface eth0 inet dhcp
hwaddress ether 01:02:03:04:05:06

Obviously you would want to choose something else for the MAC address, but it needs to be in the same format.

sudo /etc/init.d/networking restart

You will need to restart networking or reboot to take effect.

Ubuntu QQ不稳定解决方案

修改/usr/bin/qq，添加一个环境变量

export GDK_NATIVE_WINDOWS=true

修改后：
#cat /usr/bin/qq

#!/bin/sh
export GDK_NATIVE_WINDOWS=true
cd /usr/share/tencent/qq/
./qq

Whats new in Systemverilog 2009?

In 2005 there were separate standards for Verilog and SystemVerilog which are merged here with SystemVerilog 2009. There are 30+ noticeable new constructs and 25+ system task are introduced in SystemVerilog 2009.

I listed out following new constructs which are added in SV-2009.



timeunit and timeprecision

You can specify timeunit and timeprecision inside the module with single keyword.


module E (...);
timeunit 100ps / 10fs; // timeunit with optional second argument
...
endmodule

(Ch. 3.14.2.2 of LRM)


checker - endchecker

The checker is specifically created to encapsulate assertions. It can be added with the modeling code and can be instantiationed. Formal arguments of checker are inputs.

(Ch. 17)

checker my_check1 (logic test_sig);
a1: assert property (p (test_sig));
c1: cover property (!test_sig ##1 test_sig);
endchecker : my_check1

global clocking

Global clocking block is declared as the global clocking block for an entire elaborated SystemVerilog model.

global clocking @(clk1 or clk2);
endclocking

(Ch. 14.14)

Printing format

%p - displays as an assignment format.

(Ch 21.2.1.2)


%x - displays in hexadecimal format.

(Ch 21.2.1.2)

edge

It is equivalent to posedge+negedge

(Ch. 31.5)

let

This local score compiler directive replaces the other test macro like `define. A let construct may be instantiated in other expressions.
let declarations can be used for customization and can replace the text macros in many cases.

let check_grant(a, b) = assert( a ##2 b) );
check_grant(req, gnt);
(Ch. 11.13)

localparam in ANSI style header
module driver #(parameter AWIDTH = 8,
parameter DWIDTH = 8,
localparam PORT=1 >> data
);
(Ch. 22.2.3)

unique0

Keyword unique will issue a violation report if no condition matches. while keyword unique0 will not issue a violation report if no condition matches.

(Ch. 12.4.2)

Associative array size()

size() method is introduced to return number of entries in associative array like num() method.

(Ch. 7.9.1)

Queue delete()

Now you can pass specific index number inside the delete function to delete that particular index. If index is not specified then it will delete entire Q.

(Ch. 7.10.2)

Bit select and part select of an expression
Instead of...
assign t = (a & b) | (c & d);
assign val = t[7:4];

you can do...

assign val = {(a & b) | (c & d)}[7:4];
(Ch. 7.2.1)

Import package into design
package bit_pkg;
bit clk;
bit reset;
endpackage

module dut(
input bit_pkg::reset rst;
input bit_pkg::clk clock;
...
endmodule


Packet chaining, automatic package and multiple package export is also introduced in SV-2009.

(Ch. 23)

pure virtual methods

SV-2009 allows to declare pure virtual methods as well as class. It must be written in abstract class & it must be only a prototype, It must not contain any statement and must with without endtask/endfunction.


virtual class BasePacket;
pure virtual function integer send(bit[31:0] data); // No implementation
endclass
(Ch. 8.20)

pure constraint

It is allowd to declare pure constraint in abstract class. This must be implemented in extended class with the same constraint name.

virtual class C;
pure constraint test;
endclass
(Ch. 18.5.2)

Time consuming functions

Using fork/join_none, now time consuming constructs can be used inside function.

function void disp;
fork
#0 $display("%t: This is #0", $time);
#1 $display("%t: This is #1", $time);
#3 $display("%t: This is #3 and A = %x", $time, a);
a <= 8'hbb; // It allows non-blocking assignment
#2 $display("%t: This is #2", $time);
join_none
endfunction
(Ch. 9.3.2)

covergroup with sample arguments
covergroup with function sample(bit a, int x);
coverpoint x;
cross x, a;
endgroup :

cg cg1 = new;

function void F(int j);
bit d;
...
cg1.sample( d, j );
endfunction
(Ch. 19.8.1)

weak - strong

These sequence operators are introduced to simulate assertion efficiently. Assert may produce wrong message if there is a glitch in the signal. strong require that some terminating condition happen in the future, and this includes the requirement that the property clock ticks enough time to enable the condition to happen. weak do not impose any requirement on the terminating condition, and do not require the clock to tick. If the strong or weak operator is omitted, then the evaluation of the sequence_expr depends on the assertion statement in which it is used. If the assertion statement is assert property or assume property, then the sequence_expr is evaluated as weak(sequence_expr). Otherwise, the sequence_expr is evaluated as strong(sequence_expr).

The default in SV-2005 was strong while in SV-2009 is weak unless you. specified
strong.

(Ch. 16.13)

Implies and iff properties

A property is an implies if it has the following form:

property_expr1 implies property_expr2

Above form evaluates to true if property_expr1 evaluates to true, if not then

property_expr2 evaluates to true.

A property is an iff if it has the following form:

property_expr1 iff property_expr2

A property of this form evaluates to true if, and only if, either both

property_expr1 evaluates to false and property_expr2 evaluates to false or both

property_expr1 evaluates to true and property_expr2 evaluates to true.

(Ch. 16.13)

followed-by (#-#, #=#)
property s1;
##[0:5] done #-# always !rst;
endproperty
property s2;
##[0:5] done #=# always !rst;
endproperty

Property s1 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting from one of the clock ticks when done is asserted, rst shall always be low. Property s2 says that done shall be asserted at some clock tick during the first 6 clock ticks, and starting the clock tick after one of the clock ticks when done is asserted, rst shall always be low.

(Ch. 16.13)

The property operators

s_nexttime, s_always, s_eventually, s_until, s_until_with, and sequence operator strong are strong.
The property operators nexttime, always, until, eventually, until_with, and sequence operator
weak are weak.


nexttime and s_nexttime
// if the clock ticks once more, then a shall be true at the next clock tick
property s1;
nexttime a;
endproperty
// the clock shall tick once more and a shall be true at the next clock tick.
property s2;
s_nexttime a;
endproperty
(Ch. 16.13)

always - s_always

property s1;
a ##1 b |=> always c;
endproperty


property s1 evaluates to true provided that if a is true at the first clock tick and b is true at the second clock tick, then c shall be true at every clock tick that follows the second.

(Ch. 16.13)

until - until_with - s_until - s_until_with

property s1;
a until b;
endproperty

property p3;
a until_with b;
endproperty


Property s1 evaluates to true if, and only if, a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until, but not necessarily including, a clock tick at which b is true.

(Ch. 16.13)

The property p3 evaluates to true provided that a is true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing
until and including a clock tick at which b is true.

(Ch. 16.13)

eventually - s_eventually
property s1;
s_eventually a;
endproperty

The property s1 evaluates to true if, and only if, there exists a current or future clock tick at which a is true.

(Ch. 16.13.13)

not - accept_on - reject_on - sync_accept_on - sync_reject_on
property p; (accept_on(a) s1); endproperty

If a becomes true during the evaluation of s1, then p evaluates to true.


property p; (reject_on(b) s2); endproperty

If b becomes true during the evaluation of s2 then p evaluates to false.


property p; not (reject_on(b) s2); endproperty

not inverts the effect of operator, so if b becomes true during the evaluation of s2 then p evaluates to true.

(Ch. 16.13.14)

case

case can be used inside the property.

(Ch. 16.13.16)

restrict

It is constraint to the formal verification tool to do not check the property.


untyped

It is allowed to use untyped datatype inside properties.


(Deferred assertion) assert #0 - assume #0 - cover #0

Deferred immediate assertion evaluates after signal have stabilized in a time step.


Shortcut operators
##[+] is equivalent to ##[1:$]
##[*] is equivalent to ##[0:$]
<signal>[+] is equivalent to <signal>[*1:$]
<signal>[*] is equivalent to <signal>[*0:$]
(Ch. 16.7)

`define

you can pass default value in define macro.

`define MACRO1(a=5) $display(a);
(Ch. 22.5)

`undefineall

It undefines all the defined test macro which is previously declared.

`define FPGASIM
`define GATESIM
module...
....
....
endmodule
`undefineall
(Ch. 22.5)

`begin_keywords and `end_keywords

It is used to specify reserved keywords, it will give an error if implementain does not matched with version_specifier. e.g if you have specified "1800-2009" then all the previous versions of Verilog/SystemVerilog keywords can be used but if you have specified "1800-2005" then those keywords which are introduced specifically in SV-2009 those can not be used.

(Ch. 22.14)

FILE name and LINE numbers

It keeps track of the filenames of SystemVerilog source files and line nunbers in the files. which can be helpfull to source error messages and the file name. `__FILE__ expands to the name of the current input file, in the form of a string literal constant. This is the path by which the compiler opened the file, not the short name specified in `include or as the command line argument. `__LINE__ expands to the current input line number, in the form of a decimal

integer constant.

$display("Internal error: null handle at %s, line %d.",`__FILE__, `__LINE__);

file path and line number will be return which contain above message.

(Ch. 22.12, 22.13)

SYSTEM TASK


$syatem - allows operation system commands.

(Ch 20.18.1)


$global_clock returns the event statement which is written global clocking block declaration. Here it will return "clk1 or clk2".

(Ch. 14.14)


$sformatf - this system function returns the message into string. Thus string can be passed into valid function.
$fatel - $error - $warning - $info can be used outside assertion.
$assertpasson - enable execution of pass statement.
$assertpassoff - stop execution of pass statement.
$assertfailon - enable execution of pass statement.
$assertfailoff - stop execution of fail statement.
$assertnonvacuouson - enable execution of pass statement when assertion is vacuous.
$assertvacuousoff - stop execution of pass statement when assertion is non vacuous.

(Ch 20.14, 16.15.8)

$changed

It detect changes in values between two adjscent clock tics.

(Ch 20.13)

$past_gclk - $rose_gclk - $fell_gclk - $stable_gclk - $changed_gclk

It will give past sampled value of the signal with respect to global clock.

(Ch 20.13)

$future_gclk - $rosing_gclk - $falling_gclk - $steady_gclk - $changing_gclk

It will give future sampled value of the signal with respect to global clock.

(Ch 20.13, 16.15.8)

$inferred_clock - $inferred_disable - $inferred_enable

These system function are available to query assertion

(Ch. 16.15.7)

Protected envelopes

It specify a region of text that shall be transformed prior to analysis by the source language processor.

(Ch. 34)