Thursday, May 31, 2007

Compile Emacs23

The latest cvs code can use xft font. It also can use the input method in Gnome.

1. Download the S source code
sudo apt-get install ssh cvs
sudo apt-get install texinfo

export CVS_RSH="ssh"
cvs -z3 co -r emacs-unicode-2 emacs

2. Compile
sudo apt-get install build-essential
sudo apt-get build-dep emacs21
sudo apt-get install xserver-xorg-dev
sudo apt-get install xorg-dev
sudo apt-get install libncurses5
sudo apt-get install libncurses5-dev
sudo apt-get install libgtk2.0-dev

./configure --prefix=/usr --with-x-toolkit=gtk
make bootstrap
make info
sudo make install

AUTOASCIIENUM problem in Verilog-mode

When using the AUTOASCIIENUM, the last parameter should not be empty "". If you do not have identified labels on FSM state parameters, you can just have a space there: " ". With empty parameter, it will make emacs halt.



  1. Battle For Wesnoth

  2. wesnoth


    • 200+ unit types
    • 16 different races
    • 6 major factions

  3. Nexuiz

  4. nexiuz


    Several notable features of the game include

    • ability to multiplay up to 64 players
    • ability to generate bots for practice sessions
    • dynamic lighting system similar to Doom 3

  5. America’s Army

  6. americas army


  7. nemy Territory : Quake Wars

  8. quake wars


  9. Tremulous

  10. tremulous


  11. Tux Racer

  12. tux


  13. World Of Padman

  14. padman

    漫画风格的游戏,使用Quake 3引擎. 

  15. Vendetta

  16. vendetta

    第一人称视角的 MMORPG,看上去好像家园啊...

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DFT Digest - Expanding Design for Test in an Ever-Shrinking World...

I don’t know if I ever mentioned it before, but a DFT blog was not my original objective for creating an IC design oriented website. In truth, a couple of buddies and I had visions of a well-oiled EDA forum site with experienced professionals trading tricks of the trade – I was just going to be the design for test moderator. But, as always, engineers get busy or distracted, and well, we haven’t pulled it off yet.

However, there are other websites with forums out there. A couple come to mind: (this would be my preferred place to post a DFT question, as it’s run by an expert),, and also has a forum. One thing about these forums – it seems DFT still remains somewhat an esoteric art. Some of the questions: “Why DFT?”, “What is DFT?”, or “Please state all the DFT design rules and their solutions…”

Once again, design for test is often lobbed to a junior member of the design team, who more often than not, has no idea where to start. And since a majority of our engineering schools spend next to no time on test, well, here we are.

Dave Letterman counts down from 10 to 1, but I’m pretty much a bigendian digital DFT engineer, so I’m going from 9 to 0. So without further ado, I present to you my ‘Top 10 Scan Design Rules’:

9 - Melting pot: NOT! don’t mix scan cell types in a design

8 - Primary input controlled resets

7 - Primary input controlled clocks

6 - Fight the scourge of internal tri-state busses

5 - Mixing clocks and data is racy

4 - Avoid combinational feedback

3 - Remember your memories

2 - Proceed with caution (from one clock domain to another)

1 - Know your ATE

0 - Scan everything

The longer winded explanations are after the click. Have a read, and let me know what you think!

He are short explanations for my top 10 rules. I’d like to add pictures and such, and maybe I’ll do that and then post this as a permanent item on another page. When I get time… So here they are:

9 - Melting pot: NOT! don’t mix scan cell types in a design

Way back when, there were 3 flavors of scan: ‘muxed-D’, ‘clocked-scan’ and LSSD. I’ve not heard of clocked-scan for a decade. I don’t know if anyone uses it. Mux-D is the prevailing de-facto standard, and there are still pockets of LSSD (IBM, Motorola, Freescale).

But the point is – don’t mix them in a design! It won’t work. There are advantages and disadvantages to all of them as design styles, but as far as scan operation goes, they are fundamentally different. Now, before you protest, I know that it is possible for different design styles to reside in independent blocks of a larger design, such as an SoC. You can generate scan patterns separately for each. But if you’re planning a design from the top down, don’t let the designer’s think they can pick and choose…

8 - Primary input controlled resets

It is fairly common for sequential logic to generate reset signals for other areas of a device. However, if this is not dealt with explicitly, it will break the scan design. The reason is simple: If a derived reset emanates from a flip-flop that is scanned, during the shift operation, the random values being shifted through the flop will randomly reset circuitry to which it’s attached.

To remedy this, using a scan_mode signal, gate the ouput of the flop generating the reset to a safe, inactive, value. The scan_mode signal is a static signal which signifies that the device is in the mode to do scan testing. Some gate the flop off using scan_enable. This will get a better fault coverage, but may not work in capture mode due to race conditions. The absolute highest fault coverage can be obtained using a third signal in conjunction with scan_enable, and testing in two passes [1]

7 - Primary input controlled clocks

Obvious, no? Nothing’s obvious it seems, so I’ll say it: You cannot generate scan vectors for a device if you do not have complete control over the clock input for every scanned flip-flop. This is necessary for the tool to be able to reliably shift data through the chain.

What about for at-speed scan? You say, “I can’t get a XXX-MHz clock into the device! So can I use the internal PLL?” Well, yes and no. Even for at-speed ATPG, you don’t need to shift data into the device at-speed. The capture cycles, however do need to be at-speed. In this case, with a little work, you can design a gating mechanism that will allow two clock cycles to slip through from the PLL during the launch-capture phase of each scan vector.

6 - Control your tri-state busses

Internal tri-state busses should have been outlawed years ago. They may be area/power efficient, but they’re slow, and they cause havoc for ATPG. Consider the fact that the tri-state enable logic is driven by one or more scanned flops, which get random data as the ATPG shifts scan data in and out of the part. That could make for some hot action on that bus, since more than one driver may be turned on at once as the random values filter through the enable logic.

So what do we do? The first and best answer is to let the scan insertion tool to automatically take care of it. Most will.

If you must design your own protection, the brute force approach is to bring in the scan_enable signal, and during scan mode, disable all but one of the drivers on the bus while shifting data (that you leave one to drive the bus is important – if you leave none, it would result in a floating bus, another DFT no-no). When in capture mode, the bus driver enable logic will work as normal (and should be contention safe, unless designed improperly).

5 - Mixing clocks and data is racy

If, for any reason, a clock that latches data into a flop also partially determines the data being latched into it you have a potential race condition. You might see this in cases where the design uses both edges of the clock in a datapath, and the clock is used to select different data (in muxes). This situation will cause the ATPG tool to complain loudly, and will almost surely cause simulation mismatches.

To deal with this situation, you have to bring in the scan_mode signal to gate off the clock during scan, and just test for one side of the mux, or maybe insert an extra scan mode flop to control the signals that in normal mode emanate from the clock.

4 - Avoid combinational feedback

Combinational feedback is not usually a problem in good synchronous design, but could happen inadvertently if one mealy state machine directly feeds anouther (which is why it’s a good practice to register outputs of FSMs – but I digress). This feedback is a particular headache for scan design, because it can be impossible for the ATPG to be able to generate an accurate pattern.

If combinational feedback does appear in your design, the loop must be broken with a special flop inserted in the path only during scan mode.

3 - Remember your memories

Yes, I know you don’t scan your memories, but how you treat the logic around your memories will make a difference in fault coverage. Logic surrounding embedded memories (everything from the last flop to the memory inputs, and from the memory outputs to the first flop) suffer from fault coverage. It’s hard to control and hard to observe.

The first order response to this is to insert a bypass. In scan mode, the memory data inputs get muxed with the memory data outputs and are latched into the first flops after the memory. You can do this explicitly, or if you’re BISTing the memory, have the memory BIST tool do it automatically. In fact, they do a better job; they include the address bits in the bypass logic to get better fault coverage.

If you model your memory well, and mind the control signals, you may be able to convince your ATPG to test through the memory, negating the need for a bypass.

2 - Proceed with caution (from one clock domain to another)

The biggest scan chain killer, beyond uncontrolled flop inputs, is a hold time violation. Since hold time is frequency independent, you can shift data into a scan chain as slow as you want, but if you have a hold time problem, you’re screwed.

The most popular cause of hold time violations is clock skew. Designers take great pains to minimize clock skew for anything within a given clock domain. But there’s no reason to work so hard as to minimize it across all clock domains. So what if your scan chain contains flops in more than one clock domain? Use lock-up latches.

Lock-up latches are D-latches gated with the inverse of the clock that strobes the flops preceding it in the scan chain. This technique buys you another half cycle of hold time. This is a no-brainer, and actually the scan insertion tools all do this automatically. If you specify, most tools will also put a lock-up latch at the end of each chain, which may come in handy if you are combining some scan chains at a higher level of hierarchy.

1 - Know your ATE

What to you know about your target tester? How much are you willing to spend on ATE (Automatic Test Equipment)? Well, there is ATE, and then there’s ATE…

From the larger perspective, if you have money to sink into either purcahsing or renting a big-ticket tester, you may not have to work so hard on DFT. But if you’ve got an eye on the bottom line, the demands for internal test structures goes up. Make sense?

But that’s not all. From both a digital and analog perspective, it’s good to know the capabilities of the target tester so you can configure the test features to match it. Otherwise, you’re either looking for another ATE, or stuck not testing something. So when planning your scan design, think of the clock frequency that can be delivered by the tester, and how the scan vector memory is architected.

0 - Scan everything

For God’s sake, scan everything you can. for every non-scan circuit, there’s a major hassle awaiting. You have to test it somehow. Scan is the most automatic form of test available. Fight for it.

[1] VLSI Test Principles and Architectures, Pg. 76

cnBeta.COM [图]2007年Linux平台下的8款最佳游戏


ugmbbc发布于 2007-05-29 16:39:01|4930 次阅读 字体:大 小 打印预览


1. Battle For Wesnoth


* 200+ unit types
* 16 different races
* 6 major factions
2. Nexuiz



Several notable features of the game include
* ability to multiplay up to 64 players
* ability to generate bots for practice sessions
* dynamic lighting system similar to Doom 3
3. America’s Army

americas army

4. nemy Territory : Quake Wars

quake wars

5. Tremulous


6. Tux Racer


7. World Of Padman


漫画风格的游戏,使用Quake 3引擎.
8. Vendetta


第一人称视角的 MMORPG,看上去好像家园啊....

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Thursday, May 17, 2007


1. 在程序管理菜单下,不要使用左软件里的选项-删除来操作,直接按删除C键就可以了。
2. 有很多朋友把右软键设置成网络快捷键,其实待机下长按数字0键就可以进入网络。
3. 写完短信后按拨号键可以直接发送。
4. 长按功能键,会打开有已开程序的菜单,如果想退出其中一个,直接可以按“C”键退出。
5. 写短信时,需要连续输入符号时,只须按*移动你想要输入的符号,按几下5键然后再按确定键。
6. 长按菜单键,可以显示所有手机正在运行的程序。
7. 待机状态下长按#键转静音模式。
8. 长按住右软键能打开“声控命令”下的程序。
9. 写短信的时候长按住“#”键快速切换到数字输入,要输入哪个数字,可以不必切换输入法,直接常按那个数字就可以了。
10. 按住笔形键加方向键上下实现标记功能。
11. 摄像机盖滑下来自动解开键盘锁。
12. 通话时,查电话号码,按导航键中间那个确定键即可。  
13. “偷拍”,有的朋友想在拍照时取消拍照一瞬间出现的喀嚓声,你就可以在情景模式—当前情景模式—个性化选项——警告音里,将“警告音”设置成关闭,就可以了,这样拍照时就取消喀嚓声了,不过在电池电量低警告、SeleQ删除文件,还有玩普通游戏时都会没有声音了。第二种方法,在情景模式中选无声也可以达到同样效果,比上一种简单吧。
14. 字符复制法,当编写一个短信或其他文本之类,想再写一遍,但又怕麻烦,就可以象PC上用鼠标将要复制的字拖成蓝色就可以复制了,在7610上的操作是将要复制的字符前按住笔型键,然后再拖动左右方向键,将要复制的的内容拖成蓝色,然后按左功能键的“复制”,等再次到需要粘贴的地方,按住笔型键,再按右功能键的“粘贴”即可完成复制。 
15. 批量删除和批量复制法,有时候我们要删除大量消息或图片等文件的话,一个一个删除很是麻烦的,这时候可以按选项—标记—标记全部,全部的文件后面都会出现一个钩的符号,这时候再删除的话就会一次性全部删除了,还有一个是逐个标记法,就是在要删除文件的界面里按住笔型键,再按方向键上下就可以逐个选择标记,松开再进行同样的操作就是取消标记了,当然标记后一样可以进行批量复制或发送的。 
16. 快速进入法,进入功能表以后,上面的12个图标,也就是俗称的“九宫格”画面,这时候只要按键盘数键的*~9就可以对应相应位置的快捷图标进入,对应上面12个图标文件。
17. 在待机界面下长按右功能键,呼出语音界面,开始方便的语音功能。当你的情景模式的名字为标准时,在语音界面说标准这两个字的普通话,就会自动切换到标准这个情景模式。当你想拨打某个人的电话号码,直呼其名就可以了。而且,这个标准或者人名不用你事先录好,只要你的名片夹有这个名片就行,系统就会为你自动生成它的语音拨号音。
18. 国行的#这个键不是线路切换,而是情景模式的切换,在你常用的两个情景模式之间切换,需要长按,也很方便。
19. 在输入汉字的时候按*键,可以调节4个音调,可以更快捷的找到要输入的汉字。
20. 在输入英文(大,小写都可以)的时候,想打数字的话一次次的去按键真的很累,而且对键盘的损坏也比较大,除了插入数字外教大家一个更简单的方法,按住你想要输入的数字,就直接切换到你要的数字了。
21. 在想输入一排符号的时候要一次一次的去按,真麻烦~这里有个小窍门哦,选到你想要输入的符号,想打几个此符号,就按几下“5”键,之后按选择,再回到编辑栏,想输入的符号就都出来了~。
22. 在输入汉字的时候不想按*键盘去选择符号的时候,按“1”键,所有的标点都在这,按相应的次数就可以。
23. 想输入空格?更简单,输入完汉字按数字“0”键,空格就出来了。
24. 编辑完一行字后,想到下一行继续写可以吗?没问题~按三次“0”键,等待0.5秒,搞定。