Lets brush our Basics on Statistical Timing Analysis
What are the various Timing Paths in a Chip?
1. Path starting from Input Data pad and Ending at Register pin.
2. Path starting from clock-pin of a Register and Ending at Data pin of a Register(Reg-to-Reg path).
3. Path starting from output of a Register and Ends at output pad of a chip.
4. Path starting from input data pad and ends at output data pad(pure combo path).
How to time the output paths?
How to time Input paths?
How to deal with False-paths?
How to deal with Multicycle paths?
How to time the source-synchronous paths?
How many minimum modes i should qualify STA for a chip
1. Scan Shift mode
2. Scan Capture mode
3. MBIST mode
4. Functional modes for Each Interface
5. Boundary scan mode
6. scan-compression mode
How many minimum process lots , should STA be qualified.
1. Fast corner
2. Slow corner
3. Typical corner
How many minimum Timing , Should STA be qualified.
1. normal delay mode(with out applying deration)
2. On-chip variation mode (deration applied)
3. SI mode (Signal integrity cross talk impact on STA)
How many minimum STA runs should we needed to address = 6*3*3.
Any mobile phone that can send text messages can add calendar events and get agendas delivered to it. Register your phone number at Google Calendar's "Settings"->"Mobile Setup" tab, add "GVENT" (48368) to your contacts and send it a standard "quick add" line (such as "7pm Saturday Dinner at Sara's house") or one of the following codes by text message:
